Fully integrated dc offset compensation servo feedback loop

ABSTRACT

The fully integrated DC offset compensation servo feedback loop is an integrator that measures the output signal DC component, and then feeds back and subtracts the measured DC component from the input signal. A larger integrator time constant lowers the high pass corner frequency, which must be very small in order to minimize the loss of the low frequency component of the desired signals. The large time constant is achieved on an integrated circuit by the use of a class-AB fully differential opamp in conjunction with an R-2R ladder as a circuit element to accomplish an integrated large time constant integrator. The R-2R ladder is configured as a digitally programmable resistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to circuits for radio frequencytransmitters, receivers, and transceivers, and particularly to a fullyintegrated DC offset compensation servo feedback loop utilizing R-2Rresistance elements that corrects for an unwanted DC component that maybe mixed with signals in the transmitter, receiver, or transmitter.

2. Description of the Related Art

Bioinformatics institutes, which host large public collections ofmolecular biology databases, rely on fast and secure transmission oflarge amounts of biological data between their servers and their manypartners around the world. Some of these partners may be in remoteareas, forcing them to employ wireless data transfer. Also, the designof high-quality implantable miniature devices to transmit real-timephysiologic parameters from a patient's body to a bioinformatics serveris another important task for wireless communications. Such implantabledevices are expected to deliver a high level of comfort, mobility, andbetter patient care. In order to replace the low-frequency inductivecoupling techniques in implantable devices, the U.S. FederalCommunication Commission (FCC) has recently assigned the 402-405 MHzband with 300 kHz bandwidth channels for medical implant communicationservice.

This band is expected to facilitate full integration, reduce powerconsumption, enhance data transfer, and support longer communicationrange. Also, the metrological aids service has a primary allocation atthe 402-405 MHz band for medical implants. In addition, it has asecondary allocation at 402-403 MHz for the Earth exploration-satelliteservice, together with the metrological-satellite service.

In fact, penetration loss increases with higher frequencies, but itfacilitates high-level integration. Fortunately, the penetration loss atthese frequencies is relatively insignificant (10 dB with 10 mm tissuepenetration), and hence it is inherently compatible with medical implantdevices. Also, operation in this frequency range, unlike lowerfrequencies, promotes small antenna design. The availability of the402-403 MHz band, internationally accompanied with these advantages,makes this frequency band an attractive choice for the future of medicalimplant devices.

The use of wireless transmission of biological data between servers andpartners and the design of a high-quality implantable miniature devicesto transmit real-time physiologic parameters (e.g., ECG, EEG, EOG, EMG,Neural, Blood Flow, Blood Pressure, etc.) from a patient body could bethe key point in saving the patient's life. Such implantable devices areexpected to deliver a high level of comfort, mobility, and betterpatient care. The transceivers in such devices often suffer from a DCoffset problem, which could reduce the overall dynamic range and evensaturate systems at high gain levels. Adaptive digital signal-processingtechniques, along with digital-to-analog converters (DAC's), which aretypically used in wireless communications, may not be adopted inbiomedical applications due to power inefficiency.

Thus, a fully integrated DC offset compensation servo feedback loopsolving the aforementioned problems is desired.

SUMMARY OF THE INVENTION

The fully integrated DC offset compensation servo feedback loop is anintegrator that measures the output signal DC component, which is thenfed back and subtracted from the input signal. A larger integrator timeconstant lowers the high pass corner frequency, which must be very smallin order to minimize the loss of the low frequency component of thedesired signals. The large time constant is achieved on an integratedcircuit by the use of a class-AB fully differential opamp (operationalamplifier) in conjunction with an R-2R ladder as a circuit element toaccomplish an integrable large time constant integrator. The R-2R ladderis configured as a digitally programmable resistor.

These and other features of the present invention will become readilyapparent upon further review of the following specification anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a typical direct conversionfrequency-shift-keyed (FSK) transceiver supporting low powerimplementation.

FIG. 2 is a schematic diagram of a fully integrated DC offsetcompensation servo feedback loop according to the present invention foruse in the transceiver of FIG. 1, shown with a testing circuit.

FIG. 3 is a schematic diagram of the R-2-R ladder circuit employed inthe servo feedback loop of FIG. 2.

FIG. 4 is a high level block diagram showing the functionality of afully integrated DC offset compensation servo feedback loop according tothe present invention.

FIG. 5 is a plot showing transient response comparisons of the fullyintegrated DC offset compensation servo feedback loop according to thepresent invention.

FIG. 6 is a schematic diagram of a two-stage class-AB operationalamplifier employed in the servo feedback loop of FIG. 2.

FIG. 7 is a plot showing transient response comparisons of simulationsof the fully integrated DC offset compensation servo feedback loopaccording to the present invention.

Similar reference characters denote corresponding features consistentlythroughout the attached drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As shown in FIG. 1, the fully integrated DC offset compensation servofeedback loop 100 is incorporated in a direct conversionfrequency-shift-keyed (FSK) transceiver 90 supporting low powerimplementation. A half-duplex communication system (i.e., it receivesand transmits at different times) is adopted. The Phase-Locked Loop(PLL) is opened in the transmit mode of the architecture, and hence thebaseband digital data directly modulate the VCO (voltage-controlledoscillator) with an offset tone of ±Δf=70 kHz. This results in optimalselection of one of ten 300 kHz channels. In the receive mode, the VCOis a subpart in the PLL loop. The technique can easily be used for othermodulation schemes as well (e.g., amplitude modulation, frequencymodulation and phase modulation and others). However, direct modulationof VCOs for FSK signals is advantageous due to the relaxed bandwidthrequirements per channel (20 kb/s maximum data rate). An FM-modulatedsignal will be produced when the input to the VCOs is analog data.

A conceptual block diagram demonstrating the operation of the servo loopis shown in FIG. 4. The function of the servo loop 100 is to introduce aDC notch in the low pass system transfer function, eliminating the DCoffset at its output. An integrator measures the output signal DCcomponent, which is fed back and subtracted from the input signal.Proper operation of the servo loop 100 requires the implementation of anintegrator having a large time constant. A larger integrator timeconstant lowers the high pass corner frequency, which must be very smallin order to minimize the loss of the low frequency component of thedesired signals. This requires an integrator with large capacitor andresistor values, which cannot practically be implemented on anintegrated circuit chip. The servo loop 100 overcomes this practicalimplementation problem.

The servo feedback loop 100 is used for DC offset cancellation in thissystem. The servo feedback loop 100 is designed around the basebandfilter and is efficiently employed to compensate for the DC offsetassociated with self-mixing in the radio front end, as well as thatgenerated in the baseband circuits. To overcome the typical servo looprequirement of using very large capacitor and/or resistor values thatare unsuitable for integration into an IC chip circuit, the presentservo loop 100 utilizes the R-2R ladder 300 (shown in FIG. 3) as acircuit element 106 to design an integrable large time constantintegrator. The R-2R ladder circuit element 106 is configured as adigitally programmable resistor. Its equivalent resistance, seen betweenthe input and output nodes, is given by:

$\begin{matrix}{{R_{eq} = {\frac{V}{I} = {\beta \; R}}}\mspace{14mu} {where}\; \mspace{11mu} {\beta = {\frac{1}{\sum\limits_{i = 1}^{n}\; \frac{b_{i}}{2^{i}}}.}}} & (1)\end{matrix}$

Therefore, a large equivalent resistance can be achieved using arelatively very small passive resistance. For example, when b_(i)=0 fori=1, 2, . . . , n−1 and b_(n)=1, an n-bit R-2R ladder exhibits a largeequivalent resistance of (2^(n))RΩ. while actually requiring totalresistance of only (3n+1)RΩ. By replacing the passive resistor in thewell-known opamp integrator by an R-2R ladder, the transfer functionbecomes:

$\begin{matrix}{\frac{V_{o}}{V_{i}} = {- \frac{1}{{sCR}\; \beta}}} & (2)\end{matrix}$

The time constant of the integrator determines the DC notch highpasscorner frequency and the speed of the servo loop. Since the settlingtime of the servo loop is inversely proportional to the highpass cornerfrequency, the digital programmability feature of the proposedintegrator becomes advantageous. For example, the digital signalprocessing (DSP) part of the receiver can be utilized to directlyprogram the servo loop settling time to achieve a certain bit error rate(BER). The highpass corner frequency can be shifted down to achievebetter BER or up to accelerate the loop settling time, which isparticularly important for time division multiple access (TDMA)receivers. However, when the loop is designed for a specific BER orsettling time and when programmability is not needed, the switches ofthe R-2R ladder may be removed. For instance, directly connecting theleast significant 2R resistor to the opamp virtual ground and all othershunt 2R resistors to ground, the integrator original time constant ismultiplied by a factor of 2^(n) and a minimum highpass corner isachieved.

To demonstrate the operation of the proposed servo loop, the circuitshown in FIG. 2 was laid out in a 0.18 μm standard CMOS technology. Theservo loop 100 is used to introduce a DC notch in the fourth-order lowpass filter obtained by cascading two Tow-Thomas fully differentialbiquads. R-2-R ladders 106 a and 106 b each have a control input β_(s)that individually programs that R-2-R ladder's total resistance. Theservo loop occupies an area of 0.048 mm² using C_(s)=50 pF capacitors(65% of the area) and 10-bit R-2R ladder circuit elements 106 a and 106b with R_(s)=15 KΩ. Subtraction of the integrator output signal from theinput signal is simply performed by resistors R_(α) utilizing thevirtual ground property of the operational amplifier at the input port.

The exemplary operational amplifier portion of the servo loop 100 is aclass-AB fully differential opamp 600, as shown in FIG. 6, and wasemployed for low power operation and good output current drivingcapability, which enhances the speed of the servo loop 100. The opamp600 was simulated using supply voltages of ±0.25V. The opamp 600 wasoptimized to achieve at least 80 dB gain with minimum biasing current,while deriving load capacitances of 50 pF and resistances of 30 kΩ. Thisload represents the stringent load (C_(s) and ladder of R_(s)) derivedby the servo loop opamp. The optimization process has resulted in a gainof 86 dB when the opamp is biased with a total current of 1 nA, leadingto a total current of 26 nA. The opamp is compensated to have a phasemargin of better than 65°, resulting in a unity gain frequency (f_(t))of 50 kHz.

Simulated results include the frequency response shown in plot 700 ofFIG. 7. The total standby power of the servo loop is about 13 nW, whileoccupying an area of less than 0.05 mm². Simulation results obtained byusing both 10-bit and 8-bit R-2R ladders are included. DC notches withhigh pass corner frequencies of approximately 100 Hz and 310 Hz areachieved for n=10 and n=8, respectively.

Plot 500 of FIG. 5 shows the transient response of the circuit with aninput DC offset of 30 mV. It can be seen that without the servo loop,the large DC gain saturates the circuit. However, by introducing theservo loop, the DC offset is cancelled. The loop reduces the output DCoffset to less than 10 mV in 6.5 ms for n=10, and in 2.1 ms for n=8, asshown in transient response plot 500 of FIG. 5. Moreover, simulationresults using n=10 show that the value of the servo loop capacitor (Cs)can further be reduced to about 5 pF (0.8 pF), and the settling timedecreases to 690 μs (140 μs) if the required DC notch is increased to 2kHz (20 kHz).

Advances of radio frequency IC (RFIC) technology are expected to achievehigh-level integration (compared to inductive link designs), leading tominiaturization and low power consumption for MICS. Aligning with this,the proposed work has presented a design of a fully integrated analog DCcancelation scheme exhibiting low power consumption. This scheme will bean important part in the wireless implantable devices operating in theMICS service band. Also, it may be adopted for glucose-insulin controlof diabetes patients under intensive care.

The fully integrated DC offset compensation servo feedback loop 100utilizes R-2R ladder networks 300, which perform as circuit elements 106to promote the implementation of an ultra-large time constant inrelatively small area. In the evaluation, the results obtained throughthe simulation showed that the design is effective and the results areencouraging.

It is to be understood that the present invention is not limited to theembodiments described above, but encompasses any and all embodimentswithin the scope of the following claims.

I claim:
 1. A fully integrated DC offset compensation servo feedbackloop, comprising: a differential dual op amp integrated circuit having anegative input terminal, a positive input terminal, a positive outputterminal, and a negative output terminal; first and second RC circuitsconfiguring the integrated circuit as a differential integrator, thefirst RC circuit having a first digitally programmable R-2-R ladderforming the resistive component of the RC circuit, the negative inputterminal being connected between the resistive and capacitive componentsof the first RC circuit, and the second RC circuit having a seconddigitally programmable R-2-R ladder forming the resistive component ofthe RC circuit, the positive input terminal being connected between theresistive and capacitive components of the second RC circuit; whereinthe servo feedback loop is adapted for connection to a high-gain, lowpass network in summation circuitry that sums with signals having a DCoffset component input, the positive output terminal and the negativeoutput terminal of the op amp integrated circuit being adapted forconnection at first and second inputs, respectively, of the high-gain,low pass network, first and second outputs of the high gain low passnetwork being adapted for connection as differential inputs to the opamp integrated circuit through the first and second R-2-R ladders,respectively, the servo feedback loop being configured for substantiallyattenuating the DC offset component from the signals summed in thehigh-gain, low pass network.
 2. The fully integrated DC offsetcompensation servo feedback loop according to claim 1, furthercomprising means for programmably switching individual branches of saidfirst and second R-2-R ladders to ground, thereby individually adjustingtotal resistance of said first R-2-R ladder and total resistance of saidsecond R-2-R ladder.
 3. The fully integrated DC offset compensationservo feedback loop according to claim 1, wherein said differential dualop amp integrated circuit comprises a class-AB fully differentialoperational amplifier circuit.
 4. A transceiver with servo feedbackloops for compensating for DC offset in transmitted and receivedsignals, comprising: a direct conversion frequency-shift-keyed (FSK)transceiver, the transceiver having a front end modulating anddemodulating signals when transmitting and receiving signals, the frontend having a filter for transmitted signals and a filter for receivedsignals, the front end mixing an unwanted DC offset component onto thetransmitted and received signals; and a first servo feedback loopconnected across the filter for transmitted signals and a second servofeedback loop connected across the filter for received signals, each ofthe servo feedback loops having a differential dual operationalamplifier integrated circuit configured as a differential integrator,each of the operational amplifiers in the integrated circuit having anRC circuit connected thereto, each of the RC circuits having a digitallyprogrammable R-2-R ladder forming the resistive component of the RCcircuit; and wherein the differential integrator measures the unwantedDC offset and the R-2-R ladders are programmable to compensate for theunwanted DC offset.